1. Field of the Invention
The present invention relates to an information processing apparatus formed by mounting an integrated semiconductor circuit on a board. The invention relates particularly to structures of the apparatus that optimize power consumption by the integrated circuit and the amount of information processed by a semiconductor chip, and minimize the size of the integrated circuit.
2. Description of the Related Arts
Recent years have seen increases in power consumption by information processing apparatuses due to increased amounts of information to be processed by the apparatuses. It is particularly difficult for large-scale integrated (LSI) circuits to reduce power consumption while increasing the amount of information to be processed. The information processing circuits on an LSI chip can enhance their performance when a high voltage is applied thereto, but at the same time consume much power. In contrast, when a low voltage is applied, power consumption can be suppressed, but this reduces the amount of information that can be processed. Patent Document 1 (JP-A-2004-111659) and Patent Document 2 (JP-A-2007-194456) disclose multi-voltage designs for an LSI chip in which voltages are selectively applied to circuit blocks.